Integrated circuits are now transitioning from aluminum to copper metal interconnects as device generation goes beyond the 0.35 .mu.m design rules. Aluminum metal is limited for these design rules due to its inability to reliably carry current in smaller sized circuit lines. Copper has lower resistivity than aluminum so it can carry more current in a smaller area, thus enabling faster and denser chips with increased computing power. Moreover, the use of copper simplifies interconnect routing. This reduces the number of interconnect levels required and consequently removes numerous process steps which directly impact the device yield. Beyond the 0.25 .mu.m generation, current densities can reach levels that induce electromigration failure of traditional doped-aluminum conductors. The increased electromigration resistance of copper relative to aluminum overcomes this limitation, which primarily impacts the finest pitch lines found at the lower interconnect levels. Thus, copper is becoming the preferred conductor for integrated circuits.
Along with the transition from aluminum to copper is the improvement upon the dielectric insulating layers. Silicon dioxide has been traditionally used as the primary material used for insulators and has a dielectric constant of about 3.9. New insulating materials for interconnects such as low k dielectrics have been proposed, which lower interconnect capacitance and crosstalk noise to enhance circuit performance. These low k dielectrics typically comprise organic polymers and have dielectric constants less than about 3.5. Some examples of low k dielectrics include polyimide, fluorocarbons, parylene, hydrogen silsesquioxanes, benzocyclobutenes or the like.
Fabrication of integrated circuits using copper interconnects and low k dielectrics present new challenges and problems for the semiconductor manufacturer. In order to make these devices, the manufacturers commonly use a damascene process. The damascene process uses most of the same chipmaking technologies to form the interconnect as the traditional structure but differs in the way the structure is built. Instead of etching a pattern in a metal film and surrounding it with dielectric material, a damascene process etches a pattern into a dielectric film, then fills the pattern with copper. An advantage to damascene processing is that the metal etch is replaced by a simpler dielectric etch as the critical step that defines the width and spacing of the interconnect lines. One of the problems manufacturers must overcome occurs after the pattern is etched into the low k dielectric layer. The photoresist used to define the metal circuit pattern into the low k dielectric layer and any post etch residues including sidewall polymer deposition need to be thoroughly removed or stripped from the underlying layer. The existing stripping processes are not adequate for removing photoresist and post etch residues from low k dielectric surfaces.
There are two generally recognized stripping processes for removing photoresist and post etch residues remaining on the surface after the dielectrics etch is complete. The residual photoresist and post etch residues can be removed by using either a wet or a dry chemistry. Wet chemistry involves removing photoresist and post etch residues by dissolution in a suitable organic solvent. However, the cost of wet chemistry, environmental concerns with its use and contamination issues have led most manufacturers to use a dry process. One such dry process is commonly referred to as ashing.
Ashing is a technique or process by which the residual photoresist and post etch residues are exposed to a plasma. Typically, the plasma is generated from a gas mixture containing oxygen gas as one of its components. The highly reactive oxygen plasma reacts with or oxidizes the organic photoresist layer. The oxidation or combustion products resulting from the ashing operation are volatile components such as carbon dioxide and water vapor, and are carried away in a gas stream. Ashing is preferred to wet chemical removal because fewer process steps are involved, less handling of the substrates is required, chemicals and chemical handling equipment are reduced, and ashing is more environmentally acceptable.
One problem with oxygen containing plasmas is that they are generally unsuitable for use with copper and most low k interconnects. The etch selectivity of the oxygen containing plasma with low k dielectric materials is generally poor, especially for those low k dielectrics that are organic. The materials used for the photoresists are similar to those used for the low k dielectric materials. That is, both materials are easily oxidized by an oxygen containing plasma to form volatile byproducts. As a result, the low k materials are removed at roughly the same rate as photoresist by an oxygen plasma, making the ash selectivity of photoresist to low k materials close to unity. Even using very dilute oxygen mixtures, which at the same time significantly slows the ashing reaction, has not overcome this problem. The challenge is to remove photoresist and post etch residues subsequent to lithography and etch processes without affecting the pattern etched into the low k dielectric layer. Small deviations in the etched profiles can adversely impact device performance, yield and reliability of the final integrated circuit.
Copper is a readily oxidizable, ductile material and as such, is prone to oxidation with the use of oxygen containing plasmas. The build-up of copper oxide from exposure to oxygen containing plasmas is detrimental to device performance. Higher contact resistance results which impedes the flow of current through the integrated circuit. Consequently, clock speed and electromigration can be affected.
Another problem with the use of the oxygen plasma on low k dielectric layers is that the oxygen plasma has been found to change the dielectric constant during ashing. For example, it has been found that doped oxide low k materials, such as nanoglasses and aerogels, exposed to the oxygen containing plasma result in an increase in the dielectric constant. An increase in dielectric constant undesirably affects interconnect capacitance and cross talk. It is believed that this is due to the oxidation of the Si--H and Si--OH bonds to form Si--O bonds. Still further, the use of an oxygen plasma with integrated circuits having copper as the interconnect tends to oxidize the exposed copper surface and deleteriously affect device performance.
U.S. Pat. No. 4,201,579 discloses a method for removing photoresist from a substrate by a hydrogen plasma. The hydrogen plasma removes photoresist from an easily oxidizable metal surface such as gold, silver, copper and the like. The patented process is comparatively slow, not amenable to high throughput processing and not effective for removing most residues from the semiconductor wafer.
Accordingly, it is an object of this invention to provide a high throughput dry ashing process with high selectivity for removing photoresist and post etch residues from integrated devices having copper interconnects and low k dielectric insulating layers. It is a further object of this invention to provide a process that is nonoxidative such that any exposed copper interconnects are not oxidized during the ashing process. Moreover, it is another aspect of this invention that the novel ashing processes remove any native oxide that may have formed on the exposed copper interconnects, thus improving device performance.